1. Field of the Invention
The present invention relates to a phase-locked circuit.
2. Discussion of the Related Art
A phase-locked loop circuit, as illustrated in FIG. 1, includes a phase comparator 2 receiving an input signal IS and a feedback signal FBS, a filter 3 receiving an output signal CS from phase comparator 2, and a voltage-controlled oscillator (VCO) 4, which receives an output signal FS from filter 3 and provides an output signal OS of PLL 1 and controls a feedback loop to generate the feedback signal provided to phase comparator 2. The feedback loop can be, for example, a frequency divider 5 receiving output signal OS and generating feedback signal FBS.
An application of PLLs is in the implementation of low jitter oscillators for providing clock signals of accurate frequency and low jitter.
To provide such a clock signal, a quartz crystal oscillator is conventionally used. To generate a clock signal of given frequency, a quartz crystal oscillator, the natural frequency of which corresponds to the desired frequency, can be used. This solution is generally acceptable for frequencies up to 25 megahertz. However, obtaining higher frequencies, for example on the order of one hundred megahertz, presents problems, either because there is no quartz crystal oscillator that operates at the desired frequency, or because such a quartz crystal oscillator is expensive. It is thus generally preferred to use oscillators including an inexpensive quartz crystal of low frequency, for example, of 25 megahertz, and a frequency multiplier made from a PLL.
In practice, PLLs having a rather low jitter, for example, on the order of 150 picoseconds, can be found. A problem is that such a jitter, even though it is low, can be too high in some applications. Such is the case in high rate series links, illustrated for example in U.S. Pat. Nos. 5,268,937, 5,414,830, and 5,430,773, in which several 100-megahertz phase-shifted clock signals are used to drive the series transmission or reception at a higher frequency, for example, on the order of 1 gigahertz. It is then desired to obtain a jitter limited to a few tens of picoseconds, which is not possible with conventional PLLs.